www.design-reuse-china.com
Design & Reuse We Chat
搜索,选择,比较,与提供商进行安全高效的联系
You are here : design-reuse-china.com  > Hot Product
Download Datasheet        Request More Info
All Silicon IP

Overview

PCIe 5.0, 4.0, 3.1/3.0 Root Port, Endpoint, Dual-mode, Controller IP Core with Built-in Many-Channel DMA (vDMA), Legacy DMA, and Configurable AMBA AXI Interconnect

XpressRICH5-AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The XpressRICH5-AXI IP is compliant with the PCI Express 5.0, 4.0, and 3.1/3.0 specifications, as well as with the PHY Interface for PCI Express (PIPE) specification and the AMBA® AXI™ Protocol Specification.

The IP can be configured to support endpoint, root port, and dual-mode topologies, allowing for a variety of use models, and exposes a configurable, flexible AMBA AXI interconnect interface to the user. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters, including number, type, and width of AXI interfaces, PIPE interface width, low power support, SR-IOV, ECC, AER, etc. for optimal throughput, latency, size and power.

Users may optionally enable one of two built-in DMA engines based on the application requirements. PLDA is working hand in hand with multiple PHY IP vendors and Verification IP vendors to offer a range of integrated solutions for PCIe 5.0 at 32GT/s.

PLDA XpressRICH5-AXI PCIe IP is the #1 choice for ASIC, SoC and FPGA designers looking for an enterprise-class PCIe interface solution with a high-performance, reliable, and scalable AMBA 3 AXI/AMBA 4 AXI interconnect.

Features

  • Internal data path size automatically scales up or down (64-, 256-, 512- bits) based on link max. speed and width for reduced gate count and optimal throughput
  • Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs up to Gen4 x8/Gen3 x16 with same RTL code - Gen5 support pending
  • Stringent implementation of PCIe to AXI Ordering Rules and AXI to PCIe Ordering Rules guarantees AXI deadlock prevention
  • Carefully engineered AXI bridge & AXI interconnect allows full performance on AXI interfaces
  • Availability of multiple AXI Master interfaces, a key benefit for high end SSD to maximize throughput
  • Optional QuickBoot mode allows for up to 4x faster link training, cutting system-level simulation time by 20%

Deliverables

IP files​,

  • Verilog RTL source code
  • Libraries for functional simulation
  • Configuration assistant GUI

Documentation

PCI Express®, Bus Functional Model

  • Encrypted Simulation libraries

Software

  • PCI Express®, Windows x64 and Linux x64 device drivers
  • PCIe C API

Reference Designs

  • Synthesizable Verilog RTL source code
  • Simulation environment and test scripts
  • Synthesis project &, DC constraint files (ASIC)
  • Synthesis project &, constraint files for supported FPGA hardware platforms (FPGA)

业务合作

访问我们的合作伙伴页面了解更多信息

广告发布

访问我们的广告选项

添加产品

供应商免费录入产品信息

点击此处了解更多关于D&R的隐私政策

© 2018 Design And Reuse

版权所有

本网站的任何部分未经Design&Reuse许可,
不得复制,重发, 转载或以其他方式使用。