CEVA refines its Vision DSP

Sept. 27, 2016, Sept. 27, 2016 – September 2016 - CEVA announced its new XM-6 vision processor yesterday (27th Sept) and will reveal details at today's Linley Microprocessor conference in Santa Clara.

As one of the companies leading the race to provide power-efficient vision processing specifically aimed at the mobile and embedded markets (as opposed to repurposing power-hungry GPUs for workstation and datacenter usage) CEVA's designs and the traction they get in the market tell us a lot about the development and maturity of vision based equipment including AR headsets, drones and more.
CEVA claims a 3x performance improvement on vector heavy code for the new core, with a 2x boost for 'average' code, versus the previous generation chip, as well as revealing that they have for the first time included hardware dedicated to specific functions.

On the performance front, CEVA makes no mention of increased clock rate and the total compute resource (vector and scalar integer and floating point units) has not increased over the XM-4, leading to the conclusion that the improvements are due to detailed architecture changes introduced with this generation.

On the basics, XM-6 is remarkably similar to XM-4: four 32-bit scalar units linked up VLIW style to 128 16-bit integer MACs are included in the base version of the core, with a 32x16-bit floating point unit available as an option. In detail, however, there are some differences: where the 128 MACs were previously divided into two 64-wide SIMD vectors, the new core splits them differently, with one 64-wide SIMD and two 32-wide units.

At the most basic level, this allows for a convenient substitution of the optional FP units without disturbing the rest of the architecture but it also allows CEVA to better tune the vector resources to the workloads and increase the amount of available parallelism; a good proportion of the performance increase is likely to be due to that change alone. Click here to read more

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