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eTopus Technology打造面向数据中心、云、边缘和5G基站的创新SerDes技术

eTopus Technology Announces Innovative SerDes Technology for Data Center, Cloud, Edge, and 5G Base Stations

The eTopus scalable, adaptive, low-power architecture for high-speed interconnects is in production and supported by technology leader SiFive

SAN JOSE, Calif.-- February 10, 2021 --eTopus Technology, a pioneer of ultra-high-speed ADC/DSP-based SerDes for wireline applications including data center, cloud, edge, and 5G base stations, today announced the presentation of its innovative high-speed transceiver architecture at the IEEE International Solid-State Circuits Conference (ISSCC) on February 16, 2021. With support for a wide range of applications, the eTopus high-speed transceiver architecture substantially enhances system Bit Error Rate performance and Clock Data Recovery robustness while reducing system cost and power consumption for networking, storage, and 5G applications.

The ISSCC is the foremost global forum for the presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency and to network with leading experts.

eTopus to present and demo the innovative architecture at ISSCC 2021

Danfeng Xu, co-founder & VP of analog design, will present the paper titled “A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm” in the 2021 International Solid-State Circuits Virtual Conference Ultra-High-Speed Wireline session beginning on Tuesday, February 16th, 2021. The eTopus high-speed transceiver architecture supports a wide range of data rates for multiple standards, such as Ethernet, OIF CEI-112G, PCI-SIG® PCIe® Gen 1 through 6, and insertion loss from few to above 35dB.

Dr. Peter Kou, co-founder & CTO, will join Danfeng Xu to conduct a live demonstration to the conference audience. The demonstration will feature the exceptional robustness of the clock and data recovery (CDR), where the CDR remains locked at 1% BER when channel insertion loss is pushed to close to 50dB. The fast temperature tracking capability, at 10oC per minute during the temperature ramp, will also be demonstrated.

The eTopus ePHY™ IP product line, based on the presented scalable architecture, has been integrated into high-density switches for Tier-1 network, storage, 5G base station OEMs for a wide range of end-products with production in multiple process nodes. The end-products include optical module interface, chip-to-chip, backplane with multiple connectors, direct-attached cable, and flyover cable.

eTopus receives strong support from partner in the IP ecosystem



SerDes IP Cores

eTopus is excited to partner with industry leaders from the semiconductor IP ecosystem including SiFive. eTopus has selected SiFive E2-Series RISC-V Core IP to power the receiver DSP control functions.

“The SiFive E20 Core is an area and power-efficient RISC-V core to power the integrated intelligent processing behind the proprietary adaptation algorithm (eZLINK™) for SerDes application deployment,” said Harry Chan, founder & CEO of eTopus. “The SiFive E20 Core brings the entire RISC-V software ecosystem, coupled with eTopus’ extensive SerDes library through eZ-API, to provide intelligent performance tuning and smart system bring-up functionalities to support a wide spectrum of system application scenarios.”

“SiFive is delighted to partner with eTopus to use the SiFive E2-Series Core and OpenFive Ethernet, Chip-to-Chip, and Die-to-Die IP as a subsystem solution for networking and HPC verticals,” said Chris Lattner, President, Product & Engineering, SiFive. “SiFive RISC-V-based processor cores are well suited to integration with class-leading platforms such as eTopus, and optimal for data center, cloud, edge, and 5G base station applications. The SiFive E2 Core is fully integrated into the eTopus ePHY, simplifying adoption of the eTopus platform by removing separately subsequent IP licensing.”

“eTopus’ SerDes combined with OpenFive Ethernet, Chip-to-Chip, and Die-to-Die Controllers provide superior BER, and low power consumption for backplane and other applications,” said Mohit Gupta, SVP & GM SoC IP BU, OpenFive. “We are pleased to offer OpenFive Ethernet/C2C/D2D subsystem IP as a customized integrated solution to ePHY IP to save customers time and resources to focus on their SoC innovations.”

The 2021 ISSCC event is virtual, and registration for online access can be found here.

About eTopus Technology Inc.

eTopus is an innovator and technology leader in high performance, DSP-based, mixed-signal, ultra-high-speed semiconductor interconnect solutions. Our ultra-high-speed SerDes IP is adopted by global Tier-1 players to be used in networking, storage, 5G, and AI applications. eTopus is a VC-backed startup headquartered in the center of Silicon Valley where our innovations and advanced architectures are developed. Multiple locations are set up globally in USA, Europe and Greater China to provide sales, design and customer support. Our investors include SK Telecom, HK-X, corporate VCs, and cross-border funds. For more information, please visit etopus.com

eTopus Technology Announces Innovative SerDes Technology for Data Center, Cloud, Edge, and 5G Base Stations

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