Design & Reuse We Chat
关注获取最新IP SOC业界资讯

全新JESD204B 控制器及匹配 PHY,针对高密度系统提供高速、高分辨率设备互连!

Introducing JESD204B Controllers and matching PHYs for high-speed, high-resolution device interconnection for high density systems!

10th November 21. – T2MIP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s JEDEC compliant JESD204B Tx & Rx Controllers with matching PHY IP Cores which are silicon proven in major Fabs and Nodes and in mass production, fully certified, small size, low power, Simple integration, and Flexible customization.

JESD204B Tx-Rx Controllers with its matching PHY IP Core is a mechanism to achieve high-speed inter-device data transfers and deterministic latency across the serial link. JESD204B is a new 12.5 Gb/s serial interface standard for high-speed, high-resolution data converters which provides full support for the JESD204B synchronous serial interface, compatible with JESD204B.01 version specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. The host or device interface of the JESD204B can be a simple interface or can be AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or Custom protocol.

Compliant with JESD204 specification JESD204A, JESD204B.01, the IP Core supports data rate upto 12.5 Gbps and programmable clock frequency up to 12.5 GHz. It can also support 1 to 8 lanes with 1 to 8 converters per receiver and transmitter which have 1 to 32bit data width per converter. The JESD204B Controllers along with the matching PHYs can also handle different Serdes interfaces with effective device and lane identification which also enables reporting of various error statistics. Supports HD-mode and uses 10/8b decoding and encoding for SerDes synchronization, clock recovery.

The JESD204B IP Core has very low power consumption with independent per-lane power down control. With a programmable 3-tap feed forward equalizer (FFE) and Embedded receiver equalization (CTLE and DFE), it helps compensate insertion loss. It also has integrated LC-tank PLL and Ring OSC PLL making the interface processing very fast and efficient. JESD204B Tx & Rx Controller and PHY IP Cores have been used in semiconductor industry’s Industrial, Data centre, Consumer Electronics, Multimedia Devices, Medical and Military sectors…

JESD204B IP Cores

In addition to JESD204B Tx & Rx Controller and PHY IP Cores, T2M ‘s broad silicon Interface IP Core Portfolio includes USB, PCIe, HDMI, Display Port, MIPI, DDR, 10/100/1000 Ethernet, V by One, programmable SerDes, Serial ATA, and many more Controllers with matching PHYs, available in major Fabs in process geometries as small as 7nm. They can also be ported to other foundries and leading-edge processes nodes on request.

Availability: These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request / MailTo

About T2M: T2MIP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit: www.t-2-m.com

Introducing JESD204B Controllers and matching PHYs for high-speed, high-resolution device interconnection for high density systems!







© 2021 Design And Reuse


不得复制,重发, 转载或以其他方式使用。