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The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency in battery-operated consumer and mobile applications. The multi-protocol 10G PHY is small in area and provides low active and standby power while exceeding signal integrity and jitter performance of the PCI Express 3.1, SATA 6G and Ethernet standards.

The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive to further save active power.


  • Supports 1.25 to 10 Gbps data rates
  • Supports PCI Express 3.1, SATA 6G, SGMII
  • Supports x1 to x16 configurations
  • Superior signal integrity acrosslossy backplanes enabled by adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)
  • Low active and standby power
  • Spread Spectrum Clock (SSC)
  • Separate Reference Clock Independent SSC (SRIS)
  • Reference clock sharing for aggregated macro configurations
  • PCI Express Aggregation and bifurcation
  • PRBS generator and checker
  • Supports flip chip and wirebond packaging
  • Supports IEEE 1149.6 AC Boundary Scan
  • Supports -40C to 125C T

Tech Specs

Market SegmentAutomotive, Communications, Consumer Electronics, Data Processing, Industrial and Military Civil Aerospace, Others
Geometry nm16
Maturity Available on request


  • Optimized for low power and small area
  • Supports PCIe lane margining
  • Includes one, two or four full-duplex transceivers (transmit and receive functions)
  • Physical coding sublayer (PCS) blocks for PCIe, SATA, and Ethernet, supporting backchannel initialization, aggregation, bifurcation, and power management
  • Multi-lane PHY shares a single clock and support core
  • Provides high-speed serial and low-speed parallel clocks to both the transceiver and PCS.
  • Supports both internal and external reference clock connections to the PHY
  • Configurable transmitter and receiver equalization
  • Supports chip-to-chip, port side and backplane interfaces
  • Optimal receiver jitter tolerance supports a wider range of board layout designs, immunity to interference (cross talk), and reduces design constraints on board signal paths
  • Contains embedded 7-, 9-, 11-, 15-, 16-, 23- and 31-bit pseudo random bit sequencer (PRBS) for internal and external loopbacks
  • Fully controllable via the integrated logic core and the test access port (TAP)
  • Embedded bit error rate (BER) tester and internal eye monitor


  • Verilog models
  • Liberty timing views (.lib)
  • LEF abstracts (.lef)
  • CDL netlist (.cdl)
  • ATPG models
  • IBIS-AMI models
  • HSPICE models for Tx and Rx
  • Documentation








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