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Overview

Synopsys provides a broad portfolio of high-quality, silicon-proven foundation IP, including memory compilers and non-volatile memory (NVM), logic library, and test solutions, enabling system-on-chip (SoC) designers to lower integration risk and speed time-to-market.

The DesignWare® Duet Packages of Embedded Memories and Logic Libraries, part of Synopsys' Foundation IP portfolio, offer an integrated portfolio of standard cell libraries, memory compilers and memory test and repair capability. The optimized combinations of high-performance and high-density SRAMs, register files, ROMs, standard cells, and Power Optimization Kits (POKs) provide all the elements needed to implement a complete system-on-chip (SoC). Options for overdrive/low voltage, process, voltage, temperature corners (PVTs), high-density SRAMs and multi-channel logic standard cells are also available, enabling designers to achieve the highest quality of results for their SoC in their specific application.

An additional High Performance Core (HPC) Design Kit provides a suite of high-speed and high-density memory instances and logic cells specifically designed to enable SoC designers to optimize their CPU, GPU and DSP cores for maximum speed, smallest area, lowest power or an optimum balance of the three.

Tech Specs

Market SegmentIndustrial and Military Civil Aerospace, Communications, Others, Automotive, Consumer Electronics, Data Processing
Maturity Available on request

Features

  • All the elements needed to implement a complete SoC, including high-performance and high-density SRAMs, register files, ROMs, standard cells, and Power Optimization Kits (POKs)
  • High-density embedded SRAMs optimized to generate the absolute minimum area and power enable designers to achieve aggressive area and power budgets
  • Multiple levels of memory power management features. Light Sleep, Deep Sleep and Shut Down modes enable array biasing with partial periphery shut down, full periphery shut down with data retention and a complete shut down without data retention
  • Yield-optimized standard cells with multiple threshold voltage and channel length variants

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