www.design-reuse-china.com
搜索,选择,比较,与提供商进行安全高效的联系
You are here : design-reuse-china.com  > Automotive, Avionics and High safety  > Automotive Subsystems
Download Datasheet        Request More Info

Overview

LPDDR4 multiPHY: Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps - Maximum data rate is process technology dependent - Compatible with JEDEC standard DDR4 SDRAMs up to 3,200 Mbps - Compatible with JEDEC standard LPDDR3, DDR3 or DDR3L SDRAMs up to 2,133 Mbps

LPDDR4X multiPHY: Compatible with JEDEC standard LPDDR4 or LPDDR4X SDRAMs up to 4,267 Mbps

DFI 4.0 Version 2 compliant interface to the memory controller: 1:1, 1:2, and 1:4 clock modes supported - Optional dual channel DFI for independent 2-channel memories (e.g., LPDDR3/4)

Flexible channel architecture: Support for two independent LPDDR4/4X 16-bit channels via one 32-bit PHYs for reduced area and power - Support for one DDR4/3 interface

Support for 8-bit, 16-bit, 32-bit and 64-bit wide SDRAMs: 8-bit and 16-bit DDR3 (LPDDR4 multiPHY only) and DDR4 supported - 16-bit per channel LPDDR4/4X supported - 16-bit and 32-bit per channel LPDDR3 supported (LPDDR4 multiPHY only)

Flexible configuration options: LPDDR4/LPDDR4X/LPDDR3: Up to 2 DQ loads, 8 CA loads, and 4 CS loads - DDR4/DDR3: Up to 4 DQ loads and 4 ranks of CA loading - Shared AC mode that permits one address and command channel to be time division multiplexed between two independent data channels

PHY independent, firmware-based training using an embedded calibration processor: Utilizes specialized hardware acceleration engines - Automatic periodic retraining through the DFI MASTER interface

Benefits

  • Supports JEDEC standard LPDDR4X, LPDDR4, LPDDR3, DDR4, DDR3, and DDR3L (1.35V DDR3) SDRAMs
  • Support for data rates up to 4,267 Mbps (process dependent)
  • Designed for rapid integration with Synopsys Enhanced Universal DDR Memory/Protocol Controllers (uMCTL2/uPCTL2) for a complete DDR interface solution
  • PHY independent, firmware-based training using an embedded calibration processor
  • Optional dual channel architecture for LPDDR3/4/4X modes facilitates two independent channels in less area versus two independent PHYs

Tech Specs

Market SegmentAutomotive, Communications, Consumer Electronics, Data Processing, Industrial and Military Civil Aerospace, Others
FoundryTSMC
Geometry nm16
Maturity Available on request

Features

  • LPDDR4 multiPHY: Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps - Maximum data rate is process technology dependent - Compatible with JEDEC standard DDR4 SDRAMs up to 3,200 Mbps - Compatible with JEDEC standard LPDDR3, DDR3 or DDR3L SDRAMs up to 2,133 Mbps
  • LPDDR4X multiPHY: Compatible with JEDEC standard LPDDR4 or LPDDR4X SDRAMs up to 4,267 Mbps
  • DFI 4.0 Version 2 compliant interface to the memory controller: 1:1, 1:2, and 1:4 clock modes supported - Optional dual channel DFI for independent 2-channel memories (e.g., LPDDR3/4)
  • Flexible channel architecture: Support for two independent LPDDR4/4X 16-bit channels via one 32-bit PHYs for reduced area and power - Support for one DDR4/3 interface
  • Support for 8-bit, 16-bit, 32-bit and 64-bit wide SDRAMs: 8-bit and 16-bit DDR3 (LPDDR4 multiPHY only) and DDR4 supported - 16-bit per channel LPDDR4/4X supported - 16-bit and 32-bit per channel LPDDR3 supported (LPDDR4 multiPHY only)
  • Flexible configuration options: LPDDR4/LPDDR4X/LPDDR3: Up to 2 DQ loads, 8 CA loads, and 4 CS loads - DDR4/DDR3: Up to 4 DQ loads and 4 ranks of CA loading - Shared AC mode that permits one address and command channel to be time division multiplexed between two independent data channels
  • PHY independent, firmware-based training using an embedded calibration processor: Utilizes specialized hardware acceleration engines - Automatic periodic retraining through the DFI MASTER interface

Deliverables

  • Executable .run installation file includes GDSII, LEF files, LVS netlists, .lib/.db timing models, Verilog model, DRC/LVS log files, I/O IBIS Model, I/O HSPICE netlist, parameterized Verilog top-level PHY netlist files, sample Verification Environment, PHY data book, physical implementation guide, app notes, verification guide, installation guide, and implementation checklist
  • PUB includes Verilog code, Synthesis/STA constraints and scripts, sample verification environment, and data book
  • Implementation guide, application notes, and quick start manuals
  • Firmware for training, ATE test, and diagnostics
  • DDR PHY compiler
  • Support for PHY emulation
  • Generic DDR PHY FPGA prototyping model available upon request
  • Automotive Grade PHYs include automotive specific deliverables including AEC-Q100 test/characterization report, ISO 26262 safety package (FMEDA, ASIL X ready certificate) and automotive quality documentation (e.g. quality manual, DFMEA analysis report)
  • Optional deliverables include: &ndash, Signal integrity consulting services &ndash, PHY hardening consulting services &ndash, Subsystems consulting services

业务合作

访问我们的合作伙伴页面了解更多信息

广告发布

访问我们的广告选项

添加产品

供应商免费录入产品信息

点击此处了解更多关于D&R的隐私政策

© 2018 Design And Reuse

版权所有

本网站的任何部分未经Design&Reuse许可,
不得复制,重发, 转载或以其他方式使用。