With the increased use of smaller geometry semiconductor processes and FinFET transistors, the on-chip interconnect has become a prime source of timing closure issues. These issues are usually found late in the design process which causes schedule slips and delayed time-to-market. Design teams currently deal with these issues by manually inserting pipeline stages in the chip netlist through an engineering change order (ECO) process.

PIANO 2.0 solves back-end timing problems with technology that works earlier in the SoC design flow, thereby reducing schedule risk. Its new technology introduces the concept of physical interconnect distance to customers using Arteris FlexNoC and Ncore interconnect products. First, PIANO calculates the length of individual interconnect links and traces, and then uses information about the semiconductor technology process and performance targets to automatically add interconnect pipelines to close timing. Then PIANO helps validate this timing closure scheme with the physical synthesis capabilities of the Synopsys or Cadence tool chains.