The DesignWare® STAR Hierarchical System is an automated hierarchical test solution for efficiently testing system-on-chips (SoCs) or designs using multiple IP/cores, including analog/ mixed-signal IP, digital logic cores and interface IP. The STAR Hierarchical System significantly reduces test integration time by automatically creating a hierarchical IEEE 1500 network to access and control all IP/cores at the SoC level, and increases test quality of results (QoR), including optimizing test time and power through flexible test scheduling of IP and cores. With support for IEEE 1687, STAR Hierarchical System enables standardized test and control access to complex interface IPs for efficient silicon debug and diagnostics, and allows silicon debug and diagnostics by enabling IP debug test modes from the SoC level. The system's highly automated design-for-test (DFT) implementation and hierarchical IP- and core-level test enables engineering teams to cut their test integration time to a matter of days and bring their designs to market faster with lower design and test costs.