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Arm Core-Based Subsystem

All Silicon IP

Overview

Built around the Cortex A series processor cores, eSilicon has developed dual and quad Cortex processor subsystems with different L1 and L2 cache sizes that include standard functions such as Coresight PTM, GPUs, and a wide variety of interfaces such as USB, DDR3/4 I2C, I2S, PCI Express, SATA, etc. The subsystem use multiple AMBA buses (AXI, AHB, APB) making it easy to accommodate your specific IP and other specialty IP blocks such as Ethernet, 802.11 and Bluetooth. And to further reduce time-to-volume, eSilicon provides an extensive verification environment covering basic boot and CPU tests, as well as integration tests for all standard functions.

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