www.design-reuse-china.com
搜索,选择,比较,与提供商进行安全高效的联系
You are here : design-reuse-china.com  > Verification Platform  > Simulation and Verification

Perspec System Verifier

All Silicon IP All Verification IP

Overview

Frustrated by all of the manual effort and time you're spending developing complex system-level coverage-driven tests to verify your system on a chip (SoC)? Cadence® Perspec™ System Verifier automates this entire process, reducing complex use-case scenario development from weeks to just days. Compared to manual test development, you'll be able to generate 10X more tests using this platform. In addition, with its integrated debugging capability, you'll be equipped to reproduce, find, and fix complex SoC-level bugs in order to improve the overall quality of your SoC.

Because it applies an appropriate level of abstraction, Perspec System Verifier can meet the growing challenges of validating SoC performance, function, and power, especially at advanced nodes. The platform is portable, supporting reuse across

  • SoC scope, from IP to the system level, including software
  • Platforms, including FPGAs, emulators, hardware description language (HDL) simulators, virtual platforms, and silicon
  • Generated tests can be run on all Cadence Verification Suite platforms, including XceliumTM Parallel Simulator, Palladium® Z1 Enterprise Emulation Platform, and ProtiumTM S1 FPGA-Based Prototyping Platform
  • Users, including architects, hardware developers, verification engineers, and software test engineers

Using Perspec System Verifier, you ll benefit from completeness of measurement, with coverage of functionality, flows, and dependencies. You ll also gain knowledge transfer advantages, since the formal, model-based system description supports knowledge sharing between different groups, particularly hardware and software engineers.

业务合作

访问我们的合作伙伴页面了解更多信息

广告发布

访问我们的广告选项

添加产品

供应商免费录入产品信息

点击此处了解更多关于D&R的隐私政策

© 2018 Design And Reuse

版权所有

本网站的任何部分未经Design&Reuse许可,
不得复制,重发, 转载或以其他方式使用。