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128 "Hot Product" Solutions

1
12-bit, 20Msps Data Converter IP in TSMC 16FFC
Synopsys offers a comprehensive portfolio of more than 100 silicon-proven DesignWare® Data Converter IP products consisting of analog-to-digital converters (ADCs), digital-to-analog converters (DACs), auxiliary converters, video DACs (VDACs) and analog front-ends (AFEs).

2
12-bit, 320MSPS, 0.8V High Speed SAR IQ-ADC in TSMC12FFC
The DesignWare Data Converter IP products offer very high performance, high speed, ultra low power dissipation, small area use, and support for a wide range of foundry process technologies ranging from 180-nm to 28-nm.

3
AHB compliant Cache controller to meet growing demand for both energy efficient and faster SoC with NVM
  • 1. TSMC Soft IP qualification (IP9000)

4
DDR5 Controller and PHY

Cadence has prototyped the world's first IP interface in silicon for a preliminary version of DDR5 standard. A test chip contains the next-generation memory interface IP based on the industry c...


5
Design IP Portfolio
Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem.

6
DesignWare 12-bit Current-Steering IQ-DAC with 640MSPS Sampling Rate in TSMC 16FFC
With more than 15 years of experience in developing analog IP solutions, Synopsys offers a comprehensive portfolio of more than 100 silicon-proven DesignWare® Data Converter IP products consisting of analog-to-digital converters (ADCs), digital-to-analog converters (DACs), auxiliary converters, video DACs (VDACs) and analog front-ends (AFEs).

7
DesignWare 12-bit, 2.5MSPS SAR ADC for TSMC40ULP
With more than 17 years of experience in developing analog IP solutions, Synopsys offers a comprehensive portfolio of more than 100 silicon-proven DesignWare® Data Converter IP products consisting of analog-to-digital converters (ADCs), digital-to-analog converters (DACs), auxiliary converters, video DACs (VDACs) and analog front-ends (AFEs).

8
DesignWare 56G Ethernet PHY IP
The DesignWare 56G Ethernet PHY IP meets the growing high bandwidth and low latency needs of high-performance data center applications.

9
DesignWare 56G Ethernet PHY IP in 7-nm

The DesignWare 56G Ethernet PHY IP meets the growing high bandwidth and low latency needs of high-performance data center applications. Using leading-edge design, analysis, simulation, and measurem...


10
DesignWare Controller IP for CCIX 1.0 and PCIe 4.0
Synopsys' complete DesignWare CCIX IP solution consisting of controller, PHY and verification IP, delivers data transfer rates up to 25Gbps and supports cache coherency for high-performance cloud computing applications.

11
DesignWare Controller IP for CCIX v1.0

Synopsys' complete DesignWare CCIX IP solution consisting of controller, PHY and verification IP, delivers data transfer rates up to 25Gbps and supports cache coherency for high-performance clo...


12
DesignWare CSI-2 Device Controller IP
Synopsys, Inc.

13
DesignWare Data Converter IP for GF12LP Process
The DesignWare Data Converter IP offers very high performance, high speed, ultra-low power dissipation, and small area, and supports a wide range of foundry process technologies ranging from 180-nm to 12-nm.

14
DesignWare DDR4/3 PHY IP in TSMC 12FFC Process

The Synopsys DesignWare® DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applications requiring high-performance DD...


15
DesignWare DDR5/4 PHY IP for TSMC 16FFC
The Synopsys DesignWare® DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-performance DDR5/4 SDRAM interfaces operating at up to 4800 Mbps.

16
DesignWare DDR5/4 PHY IP for TSMC 7-nm

The Synopsys DesignWare® DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-performance DDR5/4 SDRAM interf...


17
DesignWare Enhanced Universal Controller for DDR4/3/2 and LPDDR4/3/2
DesignWare® DDR Memory Interface IP is a family of complete system-level IP solutions for system-on-chips (SoCs) requiring an interface to one or more of the broad range of high-performance DDR5, DDR4, DDR3/3L, DDR2, LPDDR5, LPDDR4/4X, LPDDR3, LPDDR2, and LPDDR SDRAMs or memory modules (DIMMs).

18
DesignWare HBM2 PHY IP for TSMC 16FFC
The Synopsys DesignWare® HBM2 PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), graphics, and networking ASIC, ASSP, and system-on-chip (SoC) applications requiring high-bandwidth HBM2 SDRAM interfaces operating at up to 2400 Mbps.

19
DesignWare HDMI 2.1 Audio PLL IP in TSMC 12FFC
The Synopsys DesignWare® HDMI 2.1 RX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the necessary logic to implement and verify designs for various HDMI-based applications.

20
DesignWare HDMI 2.1 RX IP for TSMC 12FFC Process

The Synopsys DesignWare® HDMI 2.1 RX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the necessary logic to implement ...


21
DesignWare IP for PCI Express 4.0 in Samsung 14LPP Process

The multi-channel DesignWare PHY IP for PCI Express® (PCIe®) 4.0 includes Synopsys' high-speed, high-performance transceiver to meet today s demands for higher bandwidth. The PHY is sma...


22
DesignWare LPDDR4 multiPHY IP for Samsung 11LPP
LPDDR4 multiPHY: Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps - Maximum data rate is process technology dependent

23
DesignWare LPDDR4X multiPHY IP for GF 14LPP
The DesignWare LPDDR4 multiPHY is Synopsys' second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-in-package applications requiring high-performance LPDDR4, LPDDR3, DDR4, DDR3, and/or DDR3L SDRAM interfaces operating at up to 4,267 Mbps.

24
DesignWare LPDDR5/4/4X PHY IP for TSMC 16FFC

The DesignWare LPDDR5/4/4X PHY is Synopsys' physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and systemin-package applications requiring high-performance LPDD...


25
DesignWare MIPI D-PHY IP for TSMC 16FFC
The increasing popularity of smartphones and other multimedia enabled mobile devices along with the demand for enhanced multimedia features are pushing device manufacturers to integrate more advanced ...

26
DesignWare MIPI D-PHY IP for TSMC 7FF

The increasing popularity of smartphones and other multimedia enabled mobile devices along with the demand for enhanced multimedia features are pushing device manufacturers to integrate more advanc...


27
DesignWare MIPI M-PHY IP for TSMC 16FFC
Synopsys silicon-proven DesignWare® MIPI® M-PHY IP is compliant with the latest MIPI Alliance M-PHY v4.1 specification and supports a wide range of high-speed interfaces for mobile applications including JEDEC Universal Flash Storage (UFS), and MIPI UniPro and Low Latency Interface (LLI) interfaces.

28
DesignWare MTP ULP NVM IP for TSMC 180-nm

The Synopsys DesignWare® Multi-Time Programmable (MTP) Ultra Low-Power (ULP) Non-Volatile Memory (NVM) IP reduces area and power while increasing the write cycle endurance specification. The NV...


29
DesignWare Multi-Protocol 16G PHY IP in TSMC 12FFC Process
The multi-lane DesignWare® Multi-Protocol 16G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth and low latency in enterprise applications.

30
DesignWare Multi-Protocol 16G PHY IP in TSMC 16FFPGL Process
The multi-lane DesignWare® Multi-Protocol 16G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth and low latency in enterprise applications.

31
DesignWare Multi-Protocol 25G PHY IP for TSMC 12FFC

The multi-lane DesignWare® Multi-Protocol 25G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY...


32
DesignWare Multi-Protocol 25G PHY IP for TSMC 12FFC
The multi-lane DesignWare Multi-Protocol 25G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications.

33
DesignWare Multi-Protocol 25G PHY IP for TSMC 16FFC
The multi-lane DesignWare Multi-Protocol 25G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications.

34
DesignWare Multi-Protocol 25G PHY IP for TSMC 7-nm
The multi-lane DesignWare® Multi-Protocol 25G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications.

35
DesignWare Multi-Protocol 25G PHY IP for TSMC 7FF
  • Supports 1.25 to 25.8 Gbps data-rate
  • Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
  • Supports x1 to x16 macro configu...

36
DesignWare Multi-Protocol 25G PHY IP in TSMC 16FF
The multi-lane DesignWare® Multi-Protocol 25G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications.

37
DesignWare PHY IP for PCI Express 4.0 in TSMC 16FFC

The multi-channel DesignWare PHY IP for PCI Express® (PCIe®) 4.0 includes Synopsys' high-speed, high-performance transceiver to meet today s demands for higher bandwidth. The PHY is sma...


38
DesignWare PHY IP for PCI Express 5.0 in TSMC 16FFC
The multi-channel DesignWare® PHY IP for PCI Express® (PCIe®) 5.0 includes Synopsys' high-speed, high-performance transceiver to meet today's demands for higher bandwidth.

39
DesignWare PHY IP for PCI Express in TSMC 12FFC

The multi-channel DesignWare PHY IP for PCI Express® (PCIe®) 4.0 includes Synopsys' high-speed, high-performance transceiver to meet today s demands for higher bandwidth. The PHY is sma...


40
DesignWare SD/eMMC PHY IP in TSMC 12FFC
The DesignWare® SD/eMMC PHY IP, compliant with the latest JEDEC and SD specifications, is a fully integrated hard macro with high-speed IOs and Delay Locked Loop (DLL)/delay lines.

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