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   VSORA is an IP provider for chipmakers designing the latest generations of digital communications systems, like 5G. Our powerful multi-core DSP architecture eliminates the need for DSP co-processors to provide a level of flexibility achievable only with software programming. A new DSP development flow allows signal processing engineers and software engineers to share the same environment and source code, dramatically accelerating time-to-market. Our mission is to meet the technical challenges by providing a state-of-the-art DSP design process and boosting the DSP computing power while simultaneously optimizing power consumption and system performance, and reducing the silicon footprint.   
7 SoCs

1
VSORA Multi-core processor
The implementation of MiMo and Beamforming for 5G or other standards is a rather challenging task that, in addition to signal synchronization, requires the use of DSP-Cores with a range of processing power. VSORA meets the challenge.

2
VSORA Single-core processor
The 5G-NR market is driving the processing power and flexibility requirements of the digital communications system to an entirely new level. Our MPU-801 single-core processor has been designed to fulfill these new requirements.

3
Artificial Intelligence Cores
The most flexible solution on the market, by giving the user the ability to select the best combination of performance, power and cost.

4
Jotunn - Generative AI Platform

The "Memory Wall" was first conceived as a theory by Wulf and McKee in 1994. It posited that the development of the processing unit (CPU) far outpaced that of the memory. As a result the ...

5
ADAS Signal Processing

VSORA s algorithm agnostic architecture makes it easy to implement the algorithms using high-level (Matlab-like) language.

6
AD1028 - Compute Companion IP Core
The modular architecture of AD1028 is well suited to meet the challenging task. With computational power of 1,028 TeraFLOPS or one PetaFLOPS running at 2GHz, AD1028 processes an eight-million pixel im...

7
Tyr Family - Autonomous Driving Companion Chips
The modular architecture of the Tyr family is well suited to meet the challenges of autonomous driving. With a computational power of 1,032 TeraFLOPS, the Tyr3 processes an eight-million cell particle...

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