The Digital Blocks DB9000AXI4 TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 4.0 AXI4 Protocol Interconnect to a TFT LCD panel. The DB9000AXI4 contains a selectable 256 / 128 / 64 / 32-bit AXI4 Master Interface and uses the AXI4 higher burst lengths & Quality of Service (QoS) capabilities to target higher resolution, higher color depth TFT LCD panels, with their resulting high frame buffer memory data bandwidth & bounded latency requirements.