The accelerator is designed for generic applications to compute 3D tensor convolved by 4D tensor to increase the efficiency by 10x.

Marquee created the microarchitecture from the specification and its own RTL design and delivered the synthesizable and lint cleaned design for verification. The unit-level and top-level verification was done by the in-house verification team.

We developed the system C model for the accelerator and ran the complete set of Resnet Models.