IGAD2DX01A is a high speed die-to-die interface PHY which transmits data through INFO RDL channels. IGAD2DX01A contains 32 Tx lanes and 32 Rx lanes per slice and supports 8 slices in one PHY. Each Tx/Rx lane can support up to 8 Gbps data rate. In summary, IGAD2DX01A offers a full-duplex data transmission with extremely low power and up to 256 Gbps data rate per slice in both directions.Each Tx/Rx slice contains PMA and PCS modules. PMA supports serialization, de-serialization, data transmission, eye training and lane repair functions. PCS provides data bus inversion, parity check and FIFO functions. One PLL is also included in IGAD2DX01A to generate 8GHz high speed clock for data transmission. IGAD2DX01A is designed and fabricated in TSMC 7nm/6nm FF CMOS process with 1.8V analog supply voltage for PLL and 0.75V analog/digital supply voltages. Independent power down mode for PLL and slices is available.