Core and analog logic may not always deploy at the same time in the same process. Maturing high performance analog typically takes longer in moving to next generation of advanced process geometries. This lagging function may slow the pace of your next generation solutions.

Credo's unique SerDes architecture has made it possible to deliver SerDes cost & power effective solutions in mature process nodes and make them available in chip form for integration with SoCs, overcoming the need for matching core logic and SerDes IP in the same process node.

Credo Nutcracker is the industry s first low-power 3.2Tbps retimer XSR-enabled high-speed connectivity chiplet with 112Gbps lane rates. The device is optimized for low power and system reach performance in next-generation multi-chip-modules (MCM) ASICs for advanced switching, compute, artificial intelligence, machine learning and CPO applications.

Nutcracker has 32 low-power lanes of 112G XSR SerDes on the host side, which communicate with the in-module system-on-chip (SOC) core ASIC. The chiplet has 32 lanes of low-power 112G MR+ reach-optimized DSP to provide the off-module interface on the line side.