|
|
||
|
||
Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers
|
|
|
|
Overview The Digital Blocks DB-DMAC-MC-AXI4-MM-STREAM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces.
Please sign in to view full IP description :
|
业务合作 |
广告发布访问我们的广告选项 |
添加产品供应商免费录入产品信息 | ||||||||
成为合作伙伴