Instruction Set Simulator (ISS) - fast, simple, easy to use, cross software development for embedded systems

The Imperas ISS is often the first simulation product used in an embedded software development project. The Imperas ISS allows the development and debug of code for the target architecture on an x86 host PC with the minimum of setup and effort. It simply requires the cross compilation of your application and running the ISS with an argument to specify the name of the application object.

Used by application software engineers who need to create software binaries on the latest architectures but who do not need platform components - the Imperas ISS works with a standard GDB debugger and GUI which makes it very easy to get started with full source code interactive debugging.

Middleware library developers can also use the Imperas ISS when building software libraries for common functions, for example multimedia standards where they code at the assembly level and make extensive use of the processor data path - the debugger/GUI shows detailed assembly and all processor registers.

Test engineers can use the Imperas ISS in a regression test environment as it can be used in batch/scripted environments as well as being used interactively.

The Imperas ISS makes use of the Imperas OVP Fast Processor Model library providing access to over 200 different instruction accurate embedded CPU model variants from the Imagination/MIPS 24Kc to the ARM Cortex-A57MPx4 quad core 64 bit processor, to the open source RISC-V. The ISS product package comes with all these CPU models and example usage of them.

Speeds of up to 1,000 MIPS can be expected on modern desktop PCs.