Menta® eFPGA Core® IP is based on a high-density embedded programmable logic architecture designed to be used in SoC, ASIC or ASSP. Using an eFPGA Core provides design flexibility and reduces time-to-market by enabling lifetime re-programmability. The technology allows logic to be changed after manufacturing, reduces the number of chip re-designs and amortizes chip development costs over several design derivatives. This is the ideal solution for semiconductor companies wanting to add configurability to their end products.
Menta IPs (IPMs) include a set of pre-configured programmable physical IPs. The IP catalog is currently available for TSMC 28HPM and GlobalFoundries 14LPP technologies, based on Mentas v4 eFPGA fabric.
The series of IP cores includes five eFPGA options that have from 7k to 60k equivalent ASIC gates, plus DSP blocks. The IP cores are delivered as hard macros with optimized arrays sizes for the embedded Logic Blocks (eLB) and embedded Customer Blocks (eCB) to address various markets and applications.