INNOSILICON MIPI D-PHY is V1.2 spec compliant and can combine either a high-speed transmitter or receiver with a low speed transceiver to support ULP, LP and HS operation. The D-PHY uses the standard PPI digital interface to simplify controller integration and supports CSI, DSI and UniPro MIPI protocols. An optional CSI controller is available.

The architecture is customizable and support s 1 to 4 lanes for increased throughput. Some of the more common customizations we have provided in the past include:

2 lanes bi-directional
Interfaces that are selectable between D-PHY, LVDS, sLVDS, HiSPi and TTL
Non-standard bus widths
Designed with ease of integration in mind. The PHY is small, low power and contains all I/Os along with primary and secondary ESD.

Efficient production testing is assured through built in BIST, loop back and Boundary scan support.