Silicon proven in mass production and test chips, leveraging a choice of DFI V2.0/V2.1/V3.0/V3.1/V4.0/ standards, the PHY can be integrated with memory controller from our own or major compatible 3rd parties. It is fully register controlled via an APB and the production testing is simplified through high-speed BIST, loopback modes, and boundary scan. The PHY combines low power consumption with its small size. This compact form factor is translated into low I/O pin count, simplifying both package substrate and PCB, while potentially allowing for board level routing with only 2 layers.