|
|
||
|
|
|
You are here : design-reuse-china.com
> FDSOI IP
> Analog Mixed Signal->Clock Generator PLL
> Clock Generator PLL
Samsung 28nm FDSOI 1.8v/1.0v APLL
|
|
|
|
Overview This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 800MHz to 3200MHz. By setting DM [3:0] and DN [11:0] to different values according to different REFIN, CLK_VCO will be locked at the multiples of input frequency.CLKO is CLK_VCO divided by DP[2:0].
Please sign in to view full IP description :
|
业务合作 |
添加产品供应商免费录入产品信息 | ||||||
成为合作伙伴