Secure Clock IP core is a PRNG-based hardware implementation of a random clock jitter injection and/or a random clock cycle inhibition. It is intended to clock feed all desired hardware, creating a secure clock domain within the System on Chip host. Each edge of the Secure Clock output is randomly delayed and/or randomly inhibited in order to make the experimental setup far more complex for the attacker. It significantly increases the needed acquisition traces used by side-channel analysis, and it fuzzes the relevant fault injection moment used by fault injection attacks.