The Xelic Optical Transport Network (OTN) Dual ODU0 Mapper/Demapper performs mapping/demapping of two 1000 BASE-X Gigabit Ethernet signals encapsulated in transparent GFP frames to/from a single OTN ODU1 frame format or two independent ODU0 data streams. Independent mapper and demapper functions are included for a single dual Gigabit Ethernet slice with support for expansion to N slices through VHDL generics.

The Dual ODU0 Mapper contains 2 GFP delineators with idle removal capability, 2 ODU0 framers (XCO0 core transmit processors) with internal FIFO and GMP mapping, and an ODTU01 multiplexer (XCO01MX core transmit processor). The GFP delineators process independent 1000 BASE-X Gigabit Ethernet signals encapsulated in Transparent GFP frames and remove all GFP idles detected. The GFP delineator identifies valid GFP Frame Core Header boundaries used for internal state machine transitions. An SSF signal is asserted when the frame delineator is not in the SYNC STATE of operation. The ODU0 transmit processors insert OTU, ODU, and OPU overhead information for generated ODU0 frames with GMP mapped payloads received from the GFP delineators. Each ODU0 framer contains an LOS input which is used to optionally generate ODU0 AIS when connected to the GFP delineator SSF output signal. Programmable payload support includes PRBS and fixed byte insertion for test purposes. The ODUT01 transmit processor performs tributary timeslot interleaving of two independent ODU0 data streams and maps them into an ODU1 frame structure. OPU1 overhead insertion includes Payload Structure Identifier (PSI), justification overhead and reserved fields. A test mode is available to insert PRBS data into any of the 2 ODU0 frame timeslots.

The Dual ODU0 Demapper contains an ODTU01 multiplexer (XCO01MX core receive processor), 2 ODU0 framers (XCO0 core receive processors) with internal FIFO and payload processing, and 2 GFP delineators with idle insertion capability. The XCO01MX Receive Processor contains a frame position counter synchronized to incoming FAS and MFAS frame indicators. OPU1 overhead is extracted from incoming frames and interpreted with various error conditions reported to an internal maskable interrupt register. Positive and negative justifications are detected and reported though internal interrupts. Tributary timeslot de-interleaving is performed on incoming frames and ODU0 frames are de-mapped and delivered to two internal FIFO structures. The XCO0 Receive Processors contains a configurable frame alignment unit with programmable options for OOF/OOM and LOF/LOM algorithm state transitions. Incoming ODU frames are de-scrambled (optional) and aligned for OTN overhead processing. Frame alignment signal overhead is interpreted to detect and report various conditions which include OOF, LOF, LOA, OOM, LOM, and LOMA. ODU AIS, ODU LCK, ODU OCI and client generic AIS maintenance signals are detected with optional interrupt generation. Payload data is extracted to an internal FIFO and delivered to the GFP delineators. The GFP delineators process independent 1000 BASE-X Gigabit Ethernet signals encapsulated in Transparent GFP frames and insert GFP idles for rate adaptation. An SSF signal is asserted when the frame delineator is not in the SYNC STATE of operation.

Various performance counters (configurable for error sync mode) are provided for the ODU0 framers and ODTU01 Multiplexer cores. All counters are configurable for saturating latch and clear operation or periodic error sync autoupdate mode. The GFP delineators do not contain counters or any internal registers.

A 16-bit generic register interface for access and configuration of internal memory mapped locations is included.