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All Silicon IP


Digital Blocks 2D Graphics Hardware Accelerator Verilog IP Cores consists of the DB9200AXI4, DB9200AXI, DB9200AHB, and DB9200AVLN. The DB9200 2D Graphics Rendering Engine IP Core (Verilog Cores DB9200AXI4, DB9200AXI, DB9200AHB) contains all the features of the DB9100, adding Geometry Drawing features. The Digital Blocks DB9100 and DB9200 2D Graphics Hardware Acceleration Engine Verilog IP Cores integrates into ASIC, ASSP, & FPGA devices, providing programmable hardware acceleration of 2D graphics function under a host processor direction.


  • Generates bitmaps from graphics instructions as well as combining existing bitmaps on and off-screen using one of 256 Raster Operations. A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT) which lay the foundation for power hardware graphics primitive operations
  • Generates characters from compressed bitmaps using its FONT Bitmap Color Expansion Unit
  • Performs Alpha Blend operations of bitmaps with its Alpha Blend unit
  • Draws lines, polygons, circles using its hardware efficient & pixel accurate Bresenham Algorithm Line Drawing Unit
  • Features

  • Line Draw Graphics Operations:
    • Pixel Draw
    • Line Draw (in any direction)
    • Poly Line Draw
    • Triangles
    • Quadrilaterals
    • Circle Draw
  • Bit Block Transfer - 3 Independent Memory Sources of data:
    • On-Screen & Off-Screen Data Block (SRC)
    • Off-Screen Fixed Pattern Data Block (PTN)
    • On-Screen visible Data Block (DST)
  • Raster Operations (ROP) performed on Block Transfers:
    • 256 Raster Operations
    • ROP0, ROP1, ROP2, & ROP3 operations
    • Includes industries most popular 15 ROPs
  • BitBLT Draw Features:
    • Pixels, Horizontal & Vertical Lines
    • Overlapping & Non-Overlapping Block Transfers
    • Solid Color Block Fills
    • FONT Monochrome Bitmap to Color Expansion, either Transparent or Opaque
    • Rotation Block Transfers: 0, 90, 180, 270 degrees
    • Block Stretch on X & Y Axis
    • Alpha Blending
    • Sprite Moves
  • Command FIFO or Descriptor Link-List Display Processing Unit:
    • Simplifies Processor Interface
    • Minimizes Processor Overhead
  • Frame Buffer & Display Features Supported:
    • Display Resolutions up to 8K x 8K
    • 4 GB Memory Range
    • 8, 16 , 24, & 32 bits-per-pixel color depths
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