Helping FPGA Designers get started with UVM

by Doulos CTO, John Aynsley, Sept. 22, 2015 – 

UVM (the Universal Verification Methodology for SystemVerilog) represents best practice in constrained random functional verification, so it is something that every digital design and verification engineer should be aware of.

However, even if you already have a sound understanding of SystemVerilog, UVM is in itself complex and challenging to learn and use; a daunting prospect, particularly if you are an FPGA designer with limited time to dedicate to verification.

The challenge of getting your first UVM project off the ground

Even assuming the highest quality training, there is still a need for further help to get started with the first project. UVM can take some time to adopt - in some areas there is more than one approach to choose from, there are optional shortcuts and new features that may or may not work for you and finding good quality advice can be hard and time-consuming in the absence of a definitive methodology. Many have observed that UVM is still in need of a "methodology", in the sense of a definitive set of rules and guidelines directing its use.

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