ARM launches next-gen CoreLink IP

By David Manners-Electronics Weekly, Oct. 27, 2015 – 

The CoreLink CCI-550 interconnect enables ARM big.LITTLE processing and a fully coherent GPU while lowering latency and increasing peak throughput. The CoreLink DMC-500 memory controller provides higher bandwidth and latency response for processors and display. Both CoreLink products have been delivered to lead partners and are available for licensing with production silicon expected by late 2016.

"An optimised path to memory is essential for a best-in-class SoC that addresses the demanding mobile market," says ARM's Monika Biddulph,

The improved support for GPU coherency in CoreLink CCI-550 enhances power management and delivers system-wide advantages. Coherency reduces development costs and time for new applications accelerated by heterogeneous processing for more efficient utilisation of compute engines. OpenCL 2.0 with shared virtual memory features and other newer programming models take full advantage of system coherency. All processors work on the same data without unnecessary cache maintenance or memory copying. This also enables a system architecture fully aligned with the HSA (Heterogeneous System Architecture) coherency standards.

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