SoC design verification at all levels is key, says Cadence

Verification technology has advanced significantly over the last few years and with today's SoC design, verification needs to be done at all levels, from the system down to the silicon in parallel, moving up and down the levels as appropriate, writes Paul McLellan, Cadence Design Systems.

By Tom Wilson, Electronics Weekly, Jan. 11, 2016 – 

The key verification technologies are formal approaches, simulation, virtual platforms, emulation and FPGA prototyping. Each technology serves a unique purpose. However, based on our system design approach, a complete verification strategy for a large system on chip (SoC) should make use of all of them.

Adapting Verification Techniques as Your Design Progresses

As a design progresses, the appropriate verification techniques to use changes; the techniques used also depend on the type of the design. When it comes to techniques, some designs are amenable to starting at a very high level of abstraction, where verification consists of running C code.

This approach works well for many visualisation algorithms, for example, which can then be compiled using high-level synthesis to get to RTL.

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