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Cadence Reference Flow with Digital and Signoff Tools Certified on Samsung's 10nm Process Technology

Reference flow enables system and semiconductor companies to accelerate delivery of designs on Samsung's second-generation 10nm process (10LPP)

SAN JOSE, Calif., Oct. 24, 2016 – SAN JOSE, Calif., Oct. 24, 2016 -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its complete suite of digital and signoff tools has been certified for Samsung Electronics' Process Design Kit (PDK) and Foundation Library on Samsung's second-generation of 10nm LPP (Low Power Plus) process. Samsung also validated the Cadence® reference flow using a quad-core design with the ARM® Cortex®-A53 processor on the 10LPP process, which was implemented with the low-power design methodology covering power-gating and memory retention, IEEE 1801 UPF2.1 power intent, and statistical on-chip variation (SOCV)-based timing closure using the Liberty Variation Format (LVF) library.

The Cadence digital and signoff tools met all of Samsung's accuracy requirements, enabling foundry customers to quickly achieve design closure and deliver large, complex FinFET designs faster with the 10LPP process. In addition, the Cadence signoff tools have been certified for tapeout using Samsung's certification criteria for baseline accuracy. The tools in the design flow include:

For more information on Cadence digital and signoff solutions, please visit https://www.cadence.com/content/cadence-www/global/en_US/home/solutions/advanced-node-solutions.html.

"Samsung and Cadence collaborated closely on this new 10LPP process reference flow to provide our mutual customers with a fast path to design closure," said Jaehong Park, senior vice president of the Design Service Team at Samsung Electronics. "Cadence's digital and signoff tools have implemented methodology innovations that enable designers to access and reap the benefits of our 10LPP process."

"Samsung's certification of the Cadence digital tools enables customers to manage and overcome complexity and deliver advanced 10LPP designs faster," said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. "Customers using the Cadence flow on Samsung's latest 10LPP process can also achieve optimal power, performance and area (PPA) to meet their aggressive time-to-market requirements."

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.

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