Process Makes Smaller, Cheaper Chips

Berkeley shows implant replacing SADP

by Rick Merritt - EETimes, Jan. 06, 2017 – 

SAN JOSE, Calif. - Berkeley researchers described a technique that they say cuts the cost and time of making leading-edge chips while creating features smaller than today's most advanced processes. The so-called tilted ion implantation (TII) process created features as small as 9 nm.

The lab work shows promise for reducing the rapidly increasing cost and complexity of making chips, which has slowed progress in Moore's law. However, it's unclear whether chip makers will adopt the technique.

"We are using argon ions to selectively damage certain parts of the silicon dioxide layer," said Peng Zheng, lead author of a paper published in the latest issue of the IEEE Transactions on Electron Devices. "It's self-aligned, tilting down with pre-existing mask features, so it doesn't have the issues of [the existing] LELE [method], where misalignment is a killer."

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