A Roadmap to Emulation of 15 Billion Gate ICs

Dylan McGrath, EETimes, Feb. 16, 2017 – 

SAN FRANCISCO-Mentor Graphics Corp. is breaking with EDA's standard procedure, rolling out an emulation platform that the company says supports a roadmap to 2022, when it will be capable of handling chip designs with 15 billion gates.

"This is not a typical EDA announcement, because we are announcing a platform that basically will carry over for five years," said Jean-Marie Brunet a senior director of marketing at Mentor, in an interview with EE Times. "We aren't going to come back in two years and say, 'Forget what we said in 2017, here's a new platform.' Everything that we are going to do for the next four to five years is around that Veloce StratoM platform."

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