Dolphin Integration sets up a large range of sponsored IPs at 55 nm to reduce SoC power consumption by up to 70%

Dolphin Integration为其客户提供了一整套基于IP的台积电55 nm uLP和uLP eFlash流程，专门设计用于帮助降低睡眠和主动模式下的SoC功耗。目前，降低SoC功耗以支持电池供电的设备一直是设计师的挑战。Dolphin Integration的代工赞助的基础知识产权为SoC设计师提供了前所未有的功能。

Grenoble, France, Jul. 17, 2017 – Dolphin Integration provides its customers with a complete set of Foundation IPs in TSMC 55 nm uLP and uLP eFlash processes; these are specifically designed to help reduce the SoC power consumption during sleep and active modes.

Lowering the SoC power consumption to support battery-powered devices has always been a challenge for designers. Dolphin Integration's foundry-sponsored offering of Foundation IPs provide SoC designers with unprecedented capabilities: an instance of 8kx32 of the SpRAM RHEA features a dynamic power consumption as low as 23.14 μA/MHz at 0.9 V, whilst supporting dual rails to enable data retention at a voltage as low as 0.6 V, with minimal leakage.

The foundry-sponsored Foundation IPs include standard-cell libraries (6T and 9T), a power management kit as well as a complete set of RAM and ROM generators, Sp/Dp/1pRF/2pRF. Designers leveraging low-power design architectures, such as powergating, dual rail, operations at low voltage, are able to reduce their SoC power consumption by up to 70 % compared to LP processes. Furthermore, the ready-to-use characterizations operating at voltages ranging between 0.9 V and 1.2 V allow to reach the targeted SoC frequency with the lowest power consumption. Evaluation kits are provided on request to assess fastly and objectively the achievable performances.

Such standard cell and memory libraries are provided with a complete set of deliverables to achieve the best Time-To-Market. Furthermore, having passed the TSMC IP 9000 Level 4 qualification in both 55 nm uLP and 55 nm uLPeF, these foundry-sponsored Foundation IPs can be used safely. Other 55 nm processes, such as 55 nm LP, LP eF and 55 nm HV, are also supported.

More than 15 companies currently rely on our offering at TSMC 55 nm to successfully design their SoCs. The most complete catalog of silicon IPs in 55 nm uLP/uLPeF is available on request to design cost-effective and ultra-low power SoCs. For more information, please check out:

Discover catalog in TSMC 55 nm uLP and uLP eFlash

For further information, sign in to MyDolphin, your private space for products evaluation kit.

About Dolphin Integration

Dolphin Integration contributes to "enabling low-power Systems-on-Chip" for worldwide customers - up to the major actors of the semiconductor industry - with high-density Silicon IP components best at low-power consumption.

"Foundation IPs" includes innovative libraries of standard cells, register files and memory generators as well as an ultra-low power cache controller. "Fabric IPs" of voltage regulators, Power Island Construction Kit and their control network MAESTRO™ enable to safely implement low-power SoCs with the smallest silicon area. They also star the "Feature IP": from ultra-low power Voice Activity Detector with high-resolution converters for audio and measurement applications to power-optimized 8 or 16 and 32 bit micro-controllers.

Over 30 years of experience in the integration of silicon IP components, providing services for ASIC/SoC design and fabrication with its own EDA solutions, make Dolphin Integration a genuine one-stop shop addressing all customers' needs for specific requests.

It is not just one more supplier of Technology, but the provider of the Dolphin Integration know-how!