Pixelworks Licenses ArterisIP FlexNoC Interconnect IP Again for Advanced Video Processing SoCs

CAMPBELL, Calif., Sept. 26, 2017 – ArterisIP, the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced that Pixelworks has licensed Arteris FlexNoC interconnect IP for use as the backbone interconnect of its advanced video processing SoCs for projectors and other video displays.

Pixelworks is an innovator in the use of network-on-chip interconnects, having first licensed ArterisIP network-on-chip interconnect IP and the Arteris memory scheduler 11 years ago. Since then, Pixelworks has used the ArterisIP FlexNoC interconnect fabric and memory scheduler as the communications backbone of multiple products.

"Pixelworks has relied upon ArterisIP for the past decade to underpin the communications infrastructure of our video systems-on-chip," said T Chan, Executive Vice President of Engineering at Pixelworks. "As the complexity of our products has grown, ArterisIP has grown with us, continually adding capabilities that increase our products' performance while helping us manage design schedules and costs. Our longstanding relationship with ArterisIP has helped us deliver cutting edge technology to our customers at a faster pace than would otherwise be possible."

"Pixelworks has been a true pioneer in advanced SoC design, being one of the first companies in the world to adopt commercial network-on-chip interconnect technology," said K. Charles Janac, President and CEO of Arteris. "We are proud of the trust that Pixelworks has placed in ArterisIP throughout our decade-long relationship."

About ArterisIP

ArterisIP provides system-on-chip (SoC) interconnect IP to accelerate SoC semiconductor assembly for a wide range of applications from automobiles to mobile phones, IoT, cameras, SSD controllers, and servers for customers such as Samsung, Huawei / HiSilicon, Mobileye (Intel), Altera (Intel), and Texas Instruments. ArterisIP products include the Ncore cache coherent and FlexNoC non-coherent interconnect IP, as well as optional Resilience Package (functional safety) and PIANO automated timing closure capabilities. Customer results obtained by using the ArterisIP product line include lower power, higher performance, more efficient design reuse and faster SoC development, leading to lower development and production costs. For more information, visit www.arteris.com

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