Open-Silicon Expands Networking IP Portfolio to Address High-Bandwidth Ethernet Endpoint and Ethernet Transport Applications

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Comprehensive IP subsystem includes Interlaken, Ethernet PCS, Flex Ethernet and Forward Error Correction IPs

Milpitas, CA,, Nov. 13, 2017 – Open-Silicon today announced the availability of a comprehensive IP subsystem targeted at high-bandwidth networking applications. The subsystem expands on Open-Silicon's existing high speed chip-to-chip Interlaken interface IP to include Ethernet Physical Coding Sublayer (PCS), Flex Ethernet (FlexE) and multi-channel multi-rate Forward Error Correction (FEC) IPs targeted for Ethernet endpoint and Ethernet transport applications. These IPs support a variety of industry standards, multiple data rates and multiple channels, thus eliminating the need for multiple IPs, all while reducing area and integration risk, and increasing performance. These highly flexible niche IPs can be easily tailored to unique customer specific application requirements, and enable fast and seamless integration of the IP into the technology of choice.

Open-Silicon's 8th generation Interlaken IP supports up to 1.2 Tbps high-bandwidth performance and up to 56 Gbps SerDes rates. This chip-to-chip interface IP is fully flexible, configurable and scalable.

The Ethernet PCS IP is compatible with different MII interfaces for connecting to the MAC and works with off-the-shelf MAC and SerDes. It supports 64b/66b encoding/decoding for transmit and receive, and various data rates ranging from 10G to 400G. It complies with the IEEE 802.3 standard and supports Ethernet and Flex Ethernet interfaces.

The Flex Ethernet (FlexE) IP features a generic mechanism that supports various Ethernet MAC rates, ranging from 10G to 400G, and works with off-the-shelf MACs. The FlexE IP supports the Optical Internetworking Forum (OIF) Flex Ethernet standard 1.0, and supports FlexE aware, FlexE unaware and FlexE terminate modes of mapping over the transport network.

The Forward Error Correction (FEC) IP achieves multi-channel multi-rate forward error correction in applications where the bit error rate is very high. It improves bandwidth by enabling 56G PAM4 SerDes integration. This single-instance IP is compatible with off-the-shelf SerDes and supports bandwidths up to 400G with the ability to connect 32 SerDes lanes. It supports the Interlaken and Ethernet standards.

"More and more enterprises and small/medium businesses are shifting their IT investments from in-house IT infrastructure to cloud-based IT services-spending on cloud services is on track to rise by over 30% in 2017," said Matthias Machowinski, Senior Research Director at IHS Markit. "In response, cloud service providers (CSPs) are heavily investing in their infrastructure, and are currently upgrading their networks to 25/100G. In anticipation of continuing growth, CSPs are already looking towards the future, and once 400G becomes available in 2018/2019, we expect them to rapidly adopt this new technology."

"Open-Silicon has been on the leading edge of networking related IPs and ASICs for over a decade," said Vasan Karighattam, Vice President of Engineering for Open-Silicon. "Expanding our IP portfolio to include support for Ethernet endpoint and Ethernet transport enables a multitude of new use cases in high-bandwidth networking.

Availability

Open-Silicon's networking IP subsystem is available now for ASIC design starts, and as a licensable IP subsystem or individual IP cores.

Visit booth #783 at SC17, in Denver, CO, November 13-16, 2017 to learn more about Open- Silicon's offerings.

About Open-Silicon

Open-Silicon is a system-optimized ASIC solution provider that innovates at every stage of design to deliver fully tested IP, silicon and platforms. To learn more, please visit www.open-silicon.com

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