Hardent IP Portfolio Supports New Features of HDMI 2.1 Specification

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VESA DSC and Reed-Solomon FEC IP cores enable HDMI controller manufacturers and IP providers to quickly implement new features of HDMI 2.1 and support higher resolution displays.

MONTREAL , Jan. 03, 2018 –  Hardent, a leading provider of video compression IP cores and a member of the HDMI Forum, today announced plans to support HDMI controller manufacturers with adopting the new HDMI 2.1 specification. Hardent's portfolio of VESA Display Stream Compression (DSC) and Reed-Solomon Forward Error Correction (FEC) IP cores will accelerate product development time and enable companies to take advantage of key new features of HDMI 2.1 to develop next-generation displays.

Version 2.1 of the HDMI specification, released November 28, 2017 by the HDMI Forum, offers a number of significant new features and bandwidth capabilities to support higher resolution displays and faster refresh rates. HDMI 2.1 provides up to 48 Gbit/s raw bandwidth, which can be used for displays supporting 8K and 10K operating at limited refresh rates or with reduced color information. In order to achieve even higher resolutions and refresh rates, HDMI 2.1 incorporates support for VESA Display Stream Compression (DSC) 1.2a, a visually lossless compression algorithm with a compression ratio of up to 3:1. With the higher link rates allowed in HDMI 2.1, DSC makes resolutions of over 8K with HDR 10-bit color possible, at refresh rates of both 60Hz and 120Hz.

In contrast to other bandwidth reduction methods, such as 4:4:4 to 4:2:2 or 4:2:0 color subsampling, VESA DSC compression preserves the color integrity of the original image. DSC can also be used with the previous HDMI standard link rates of 3 and 6 Gbit/s. This means that HDMI cables supporting earlier versions of the HDMI standard can also achieve higher resolutions and frame rates through the use of compression, making display resolutions above 4K at 120Hz possible.

To achieve higher throughputs, HDMI 2.1 uses a new packet-based link layer. This layer converts the clock and three data lanes of original HDMI TMDS mode to three or four self-clocked links that can be operated at up to 12 Gbit/s. A versatile packet mode maps video, either uncompressed or compressed with DSC, audio, and data over the link. A Forward Error Correction (FEC) algorithm is used to correct possible transmission errors to ensure an error free transmission of the packets over the HDMI links.

Hardent's IP portfolio offers VESA DSC 1.2a encoder and decoder IP cores, as well as HDMI 2.1 Forward Error Correction (FEC) receiver and transceiver IP cores. "Using Hardent's IP blocks can significantly reduce development time and cost for semiconductor and HDMI controller manufacturers migrating from HDMI 2.0 and earlier to the new 2.1 specification," explains Alain Legault, VP IP Products at Hardent. "Our customers benefit from our extensive knowledge of implementing VESA DSC and FEC algorithms across a wide range of industries and product applications."

Hardent will be showing a live demo of Display Stream Compression at the HDMI Booth (South Hall 1, Booth 20542) during CES 2018. For more information about Hardent's VESA DSC and FEC IP cores for HDMI 2.1, visit Hardent's website.

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