eSilicon Tapes Out 7nm neuASIC IP Platform Test Chip

Chip validates latest release of IP to support artificial intelligence ASICs

SAN JOSE, Calif. — May 7, 2019— eSilicon, a leading provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today the tapeout of a 7nm test chip to validate the latest neuASIC™ IP platform release. eSilicon’s neuASIC IP platform provides a library of IP that supports a wide range of functions found in artificial intelligence applications. The IP is verified to be compatible and supports algorithm-specific customization as well as a validated integration architecture through eSilicon’s ASIC Chassis.

IP on the test chip includes specialized memory and compute blocks to support near-memory compute applications. These include specialized low power memory for interfacing with multiply-accumulate functions (MACs) as well as large embedded SRAMs supporting multiple ports. The large (GIGA) memory supports WAZPS (word all zero power saving) and various sleep modes for standby power reduction. The compute blocks include several MAC blocks, low power standard cells, transpose memory functions and a convolutional neural network engine. Low-power data movement IP (cross-bar) are also included as well as IP for support functions such as GPIO, PLL and BIST.

“Our neuASIC IP platform has received a very strong reception,” said, Patrick Soheili, vice president, business and corporate development at eSilicon. “Some of the largest consumers of AI technology in the world, as well as many high-profile AI startups have engaged with us to dig deeper into our neuASIC IP platform. This new test chip will provide silicon data to support that process.”

You can learn more about eSilicon’s neuASIC IP platform here, or contact your eSilicon sales representative directly or via sales@esilicon.com.

AbouteSilicon
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC™ platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets. www.esilicon.com

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