Digital Blocks DMA Controller Verilog IP Core Family Extends Leadership with enhancements to AXI4 Memory Map and Streaming Interfaces

GLEN ROCK, New Jersey, January 2, 2023 – Digital Blocks, a leading developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for system-on-chip (SoC) ASIC, ASSP, & FPGA developers, announces enhancements to DMA Controller Verilog IP Core offerings with capabilities to stream data to and from memory such as between Network Interfaces and System Memory.

Digital Blocks DMA Controller IP Core family members contain feature-rich, system integration-level features. Current DMA Controllers are as follows:

• AXI4 Multi-Channel DMA Controller, 1-16 Channels, Scatter-Gather, high performance, many user feature-rich, system integration-level options
• AHB5 Multi-Channel DMA Controller – targets latest AHB Interconnect
• AXI4-Stream to Memory driven by DMA Controller
• Memory to AXI4-Stream driven by DMA Controller
• UDP/IP Hardware Stack with DMA Controller
• DMA Controller with Interfaces to PCIe

Price and Availability

The Digital Blocks DMA Controller IP Core family is available in synthesizable Verilog, along with a comprehensive simulation test suite, datasheet, and user manual. Full press release here: DMA-Controller-Announcement-2023.pdf For further information, product evaluation, or pricing, please go to Digital Blocks at https://www.digitalblocks.com/dma.html

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