Imperas就RISC-V软件开发签署三方合作协议

Imperas in RISC-V three way deal

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Imperas Software has signed a three-way collaboration with MIPS and Ashling across all aspects of RISC-V software development.

www.eenewseurope.com/, Mar. 13, 2023 – 

The three will use the Imperas reference models for the MIPS eVocore P8700 RISC-V Multiprocessor, together with Ashling's RiscFree SDK tools to extend the level of support for developers from pre-silicon to prototype devices to end users.

Imperas from the UK and Ashling and MIPS from the US are all at the Embedded World (EW2023) exhibition in Nuremberg Germany, this week.

The fast Imperas Reference Models provide a programmer's view of the hardware running full application-class workloads and operating systems, while the Ashling tools provide the toolchain support including an IDE, compiler and software debugger.

During initial SoC concept development, virtual platforms assist with multicore architectural exploration. Key SoC project milestones are supported with OS porting, driver development, and applications-grade software development, often many months before silicon prototypes are available. Further, to help accelerate end device adoption and deployment, Fixed Platform Kits (FPKs) can be used as virtual development boards for end users of new SoC devices.

The Imperas RISC-V reference models are configured as programmer's view models of the MIPS eVocore P8700 for virtual platforms and software development. The new MIPS eVocore CPUs – the first MIPS CPUs based on the RISC-V instruction set architecture (ISA), provide a flexible foundation for high-performance heterogeneous computing.

The Imperas reference models, having been used as a golden reference model during the verification of the processor core, are now well qualified as a dependable reference for software development.

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