Scale FD-SOI to 7nm? Yes, We Can

By Anne-Françoise Pelé, EETimes Europe (November 16, 2023)

Why set the target at 10 nm when you can aim further?

During the consultative phase leading up to the Chips Act, the EU asked its three champions of microelectronics research—CEA-Leti, imec and Fraunhofer—how they might support the European challenge of doubling production by 2030, seeking their recommendations for a strategic roadmap. Their proposal included establishing a fully depleted silicon-on-insulator (FD-SOI) pilot line in Grenoble, France, to help scale FD-SOI process technology to 10 nm.

Why set the target at 10 nm when you can aim further? European Commissioner Thierry Breton raised the ante, proposing to scale FD-SOI down to 7 nm. Criticism was rife, but he persisted.

“If we set ourselves the ambition to get there, and to get there together at the European level, we will get there,” Breton said in September at the inauguration ceremony for Soitec’s SiC wafer fab in Bernin, near Grenoble.

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