True Circuits在DAC重磅推出：低抖动Digital Ultra+ PLL

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Will also showcase other high-performance PLL, DLL and DDR PHY IP and offer daily presentations and demos of its powerful JSPICE™ Design Environment (JDE™).

Jun. 20, 2025, Jun. 20, 2025 – 

Who

True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) for the semiconductor, systems and electronics industries.

What

At the 62nd Design Automation Conference (DAC), TCI will introduce an improved, state-of-the-art digital LC PLL that includes an innovative digital control algorithm that cuts the lock time by as much as 70% over previous versions, while directly controlling the loop bandwidth accurately (0.1% of Fref or better) and consistently across PVT variations through continuous background loop-gain calibration. Called the Ultra+, this PLL is highly programmable so one PLL can be used for all applications on a SoC. It has ultra-low jitter performance (<100fs) for the most demanding SerDes and ADC reference clocks and ultra-wide multiplication range (1-250,000) to support reference clocks from 32KHz to 1GHz. The Ultra+ PLL also offers precise frequency control with a least 26 fractional bits (at least 10 precise) for extremely high fractional-N resolution. It can also generate precise and adjustable frequency spreading with programmable rate and depth to meet tight FCC requirements. The Ultra+ PLL does all this while drawing low power from a compact size. The PLL can be delivered as synthesizable or hardened IP with a modular design, so customers can build their own features easily and safely using hard macros and stock Verilog code.

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