牛芯半导体PCIe IP技术升级：跨越PCIe 3.0至5.0，筑牢芯片互连根基

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www.design-reuse.com – Apr. 06, 2026 –

As the "data highway" connecting core components such as CPU, GPU, and NVMe solid-state drives in SoC chips, the performance and stability of the PCI Express (PCIE) interface IP directly determine the communication efficiency of the entire system. In today's era of booming demand for AI, high-performance computing (HPC), and data centers, high-speed and reliable I/O interconnection has become the key to the breakthrough of chips.

Relying on its profound technical accumulation in the field of high-speed interfaces, NiuXin Semiconductor has successfully overcome the core technologies of the entire series from PCIE 3.0 to PCIE 5.0 and formed a complete solution. At present, NiuXin's PCIE IP has been successfully adopted by several well-known domestic chip manufacturers, and some projects have completed tape-out verification.

PCIe 5.0 IP: Breaking through at a rate of 32GT/s to strengthen the computing power foundation

Facing the extreme demand for bandwidth in AI large model training, high-performance computing, and next-generation data centers, PCIe 5.0 has increased the transmission rate to 32GT/s, becoming the key to breaking through the system performance bottleneck. The PCIe 5.0 IP independently developed by NiuXin Semiconductor adopts an advanced analog front-end architecture and digital signal processing algorithms, effectively overcoming the signal loss and noise interference during high-speed transmission, and providing a self-controllable high-speed interconnection solution for high-end chips.

NiuXin Semiconductor's PCIe 5.0 IP integrates a high-performance clock data recovery (CDR) circuit and adopts multi-tap transmitter feed-forward equalization (FFE) and receiver decision feedback equalization (DFE) technologies to construct a complete link equalization solution, which can effectively improve the channel margin and support continuous link equalization, ensuring the stability of data transmission.

Currently, this IP has completed silicon verification based on the mainstream 12nm advanced process node. The insertion loss compensation ability, bit error rate, and various compatibility indicators all meet the protocol standards and have been adopted by leading chip customers. It is being applied in flagship projects such as AI computing power super nodes, data acceleration cards, and high-end SSD controllers, helping to boost the performance of high-end computing power chips.

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