Analog Bits 将于 2026年6月24日 亮相 EE Times 线上研讨会，探讨"芯粒可扩展之路"

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www.design-reuse.com – Jun. 18, 2026 –

Alan Rogers, Analog Bits President and CTO, and Mahesh Tirupattur, Analog Bits CEO, to participate.

When: June 24-25, 2026. Location: Virtual. Explore the future of scalable semiconductor design at "EE Times Presents: The Road To Chiplet Scalability." Analog Bits President and CTO, Alan Rogers, and CEO, Mahesh Tirupattur, will be among industry leaders discussing chiplet architectures, advanced packaging, interconnect technologies, 2D/3D integration, and scalable platforms powering AI, cloud, and high-performance computing.

Power and Thermal Efficiency Challenges of Chiplets

Presented by Alan Rogers, President and CTO, Analog Bits. As advanced semiconductor technologies move into FinFET and Gate-All-Around (GAA) nodes, power is emerging as a defining architectural constraint for next-generation chiplet systems. This fireside chat explores how intelligent power and thermal management is reshaping chiplet architecture through real-time telemetry, adaptive voltage regulation, distributed sensing, and closed-loop optimization.

Panel Discussion: Scaling Chiplets Without Breaking the System – Where are the Limits?

This panel discussion, moderated by Nitin Dahad, Executive Editor of EE Times, explores where the limits are today in scaling multi-die designs and what it will take to push beyond them. Panelists include Sachin Gandhi (Retym), Sailesh Kumar (Baya Systems), Mahesh Tirupattur (Analog Bits), and Dave Welch (AttoTude).

Register at: EE Times "The Road to Chiplet Scalability"

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