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Agile Analog 携手 Xiphera,共同应对后量子密码 (PQC) 技术挑战
www.design-reuse.com – Jun. 17, 2026 –
Combining analog security IP and digital cryptographic IP for comprehensive defense
Cambridge, UK. Agile Analog, the analog security IP specialist, has announced a collaboration with Xiphera, the hardware-based cryptographic solutions expert. The integration of Agile Analog's agileSecure anti-tamper sensor IP and Xiphera's digital cryptographic IP cores creates a unified defense solution for the next generation of semiconductor security. This is particularly important as the industry transitions to Post-Quantum Cryptography (PQC).
According to Chris Morrison, VP Product Marketing at Agile Analog: "As the industry prepares for the post-quantum era, we can no longer afford to view digital cryptography and physical security as separate silos. SoC designers face an increasingly complex threat landscape, demanding security solutions that are both secure and easy to integrate."
"Customers look for trusted technology partners that can provide solutions for multiple layers of security architecture," says Tommi Lampila, CRO at Xiphera. "By combining our expertise, we are able to help our customers build comprehensive cryptographic and fault protection solutions for their semiconductor designs."
Xiphera's PQC algorithms offer essential, mathematically robust protection against future quantum threats. While cryptographic algorithms protect data and communications, semiconductor devices must also be protected against physical attacks and tampering. Combining Xiphera's quantum-resistant cryptographic IP with Agile Analog's anti-tamper sensor IP provides a comprehensive security approach for modern semiconductor designs.
Chris Morrison concludes: "A truly secure semiconductor design requires safeguarding both the digital and physical domains. By combining Xiphera's world-class cryptographic IP with our advanced analog glitch and tamper detectors, we eliminate these vulnerabilities. Together, we provide designers with a complete, multi-layered security subsystem that protects chips from both remote cyber threats and direct physical attacks."



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