CAST推出用于汽车传感器接口的PSI5-HOST IP核

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www.design-reuse.com – Jun. 30, 2026 –

Configurable host controller brings robust two-wire PSI5 sensor connectivity to custom automotive SoCs and FPGAs

Woodcliff Lake, NJ — June 30, 2026 — Semiconductor intellectual property provider CAST today announced the PSI5-HOST Peripheral Sensor Interface 5 Host Controller IP core, a configurable digital controller that lets ASIC and FPGA developers integrate the ECU side of PSI5 automotive sensor communication directly into their own devices.

PSI5 is a specialized automotive sensor interface proven in safety-related systems such as airbag and crash-sensor networks. It is also applicable to selected braking, chassis, suspension, steering, and automotive test and validation equipment designs. It carries power and data over a two-wire link, helping automotive developers connect distributed sensors with deterministic timing, high robustness, and low implementation cost.

The new CAST PSI5-HOST core supports PSI5 Specification v2.3 and is backward compatible with PSI5 v1.3. It supports both synchronous and asynchronous communication, sensor-to-ECU Manchester-coded upstream messaging, and ECU-to-sensor downstream communication using tooth-gap or pulse-width encoding.

"Automotive SoC developers often need to integrate reliable, timing-aware sensor interfaces without depending on a specific MCU family or external controller device," said Peter Dumin, product manager at CAST. "PSI5-HOST gives them a configurable, silicon-proven PSI5 controller that fits cleanly into custom ECU, sensor-interface, and safety-related automotive designs."

Configurable PSI5 Connectivity for Automotive SoCs

PSI5-HOST can be configured for up to eight independent PSI5 channels, with up to six timing slots per channel. The core supports 125 kbps and 189 kbps upstream operation, with independent channel configuration, Manchester decoding and error detection, and downstream communication for sensor control. Receive buffering is also configurable: designers can use off-core SRAM or internal flop-based memory, with up to 32 receive frames per channel and operation as either FIFO or random-access buffers.

Safety-Oriented Architecture and Integration Support

The PSI5-HOST architecture includes safety-oriented features useful in ISO 26262-related development, including parity-protected control/status registers and data buffer, CRC and parity handling, programmable glitch filtering, watchdog timing-slot monitoring, and 24-bit timestamp generation with an internal or external time base. The host processor accesses the core through a configurable AMBA® APB2/APB3/APB4/APB5 CSR interface. For projects targeting ASIL-classified systems, CAST offers an optional ISO 26262 ASIL-D documentation package including a Safety Manual and FMEDA.

Complements CAST's Automotive Interface Portfolio

PSI5-HOST joins CAST's broad automotive interface IP portfolio, which includes CAN, CAN FD, CAN XL, LIN, SENT, MSC/MSC-Plus, SafeSPI, TSN Ethernet endpoint and switch cores, and other interface and processing IP for automotive SoC and ECU developers. Sample implementation results and additional technical details are available on the PSI5-HOST IP core product page. For pricing, evaluation options, or technical information, contact CAST at info@cast-inc.com.

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