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Synopsys' complete DesignWare CCIX IP solution consisting of controller, PHY and verification IP, delivers data transfer rates up to 25Gbps and supports cache coherency for high-performance cloud computing applications. The Cache Coherent Interconnect for Accelerators (CCIX) standard was created to enable hardware accelerators and processors to maintain cache coherency across shared memory in a heterogeneous multi-processor system, and leverage PCI Express 4.0 line rates up to 16Gbps with extended speed modes to accelerate speeds up to 25Gbps.

The CCIX IP is built on the silicon-proven DesignWare IP for PCI Express (PCIe) 4.0, which has been validated in over 1500 designs and shipped in billions of units, enabling designers to lower integration risk while accelerating adoption of the CCIX standard. Synopsys is a contributing member of the CCIX Consortium.


  • Solution consists of digital controller, PHY and verification IP
  • Supports all required features of the CCIX transport specification plus extended speed mode (ESM) at 20Gbps and 25Gbps with targeted process ports at 16-nm and smaller
  • Supports all required features of the PCIe 4.0 (16 GT/s), 3.1 (8 GT/s), 2.1 (5 GT/s) and 1.1 (2.5 GT/s), and 8-, 16-, or 32-bit PIPE specifications
  • Controller provides reliability, availability, and serviceability (RAS) features, in addition to debug capabilities, error injection and statistics monitoring
  • Low-power, compact PHY optimizes performance across voltage and temperature variations, and delivers superior signal integrity and jitter performance
  • Verification IP offers configurable environments, complete portlevel checks and system-wide coherency checks

Tech Specs

Market SegmentAutomotive, Communications, Consumer Electronics, Data Processing, Industrial and Military Civil Aerospace, Others
Geometry nmall
Maturity Available on request


  • Supports all required features of the CCIX transport specification plus Extended Speed Mode (ESM) at 20GT/s and 25GT/s
  • Supports all required features of the PCI Express 4.0, 3.1, 2.1 and 1.1 specifications
  • Supports up to sixteen 25.0, 20.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes
  • Available in 128-, 256- or 512-bit datapath widths for maximum flexibility
  • Supports PHYs with 8-, 16-, or 32-bit interfaces including variable clock and variable data modes
  • Full transaction layer, data link layer and physical layer
  • Application interfaces include the time-proven Synopsys native interface with extensions for CCIX, or the optional ARM® AMBA® 4 AXI, or AMBA 3 AXI application interface with extensions for CCIX
  • Includes CCIX Transport DVSEC configuration space
  • Optional embedded DMA controller with up to 8 read and 8 write channels for high throughput with minimal SoC resource overhead
  • Configurable and efficient retry buffer design for low latency and area
  • Supports automatic lane reversal and polarity inversion
  • Supports the full range of maximum packet sizes (128B to 4KB) and read request sizes (128B to 4KB) Performs flow-control credit management, configurable for infinite credits for any traffic type
  • Supports legacy INTx, MSI, and MSI-X interrupt semantics
  • Configurable filtering rules for posted, non-posted and completion traffic
  • Configurable BAR (up to 6) filtering, IO filtering, configuration filtering and completion lookup/timeout Support for multiple application clients
  • In-band and out-of-band access to configuration space registers and external user application registers with local bus controller
  • Expansion ROM, VPD, and Device Serial Number support
  • Supports optional ECNs


  • The coreConsultant utility to guide designers through the installation configuration, architectural exploration, verification, and implementation of the IP
  • Verilog RTL code
  • Example PHY interfaces
  • ASIC and FPGA synthesis scripts
  • Verification environment
  • Synopsys Verification IP for the PCI Express
  • Documentation: release notes, installation/integration guide, application notes, user manual








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