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Overview

The DesignWare LPDDR5/4/4X PHY is Synopsys' physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and systemin-package applications requiring high-performance LPDDR5, LPDDR4, and LPDDR4X SDRAM interfaces operating at up to 6400 Mbps. With flexible configuration options, the LPDDR5/4/4X PHY can be used in a variety of mobile applications supporting LPDDR5 and/or LPDDR4/4X SDRAMs, precisely targeting the specific power, performance, and area (PPA) requirements of these systems.

Optimized for high performance, low latency, low area, low power, and ease of integration, the LPDDR5/4/4X PHY is provided as hardened IP components (macrocells) to facilitate the following types of signals:

- Single-ended Command/Address (C/A) and Data (DQ) signals

- Differential signals (clock, data strobe, and WCK signals)

- CMOS logic-level based C/A signals

The macrocells include fully integrated IOs and are easily assembled into a variety of configurations supporting a wide range of SoC DRAM interface requirements. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB) that features Synopsys' unique firmware-based training capability. In addition to training the interface after boot-up, the PUB contains the configuration registers for the PHY, performs periodic delay line compensation against voltage and temperature drift, performs DRAM retraining, and facilitates ATE testing and interface diagnostics. The LPDDR5/4/4X PHY includes a DFI 5.0 interface to the memory controller and can be combined with the DesignWare LPDDR5/4/4X Controller for a complete DDR interface solution.

Benefits

Supports JEDEC standard LPDDR5, LPDDR4 and LPDDR4X SDRAMs Support for data rates up to 6400Mbps Designed for rapid integration with Synopsys’ LPDDR5/4/4X controller for a complete DDR interface solution DFI 5.0 controller interface PHY independent, firmware-based training using an embedded calibration processor Optional dual channel architecture for LPDDR5/4/4X modes, which facilitates two independent channels in less area versus two independent PHYs Support for DFI-based low power modes and lower power sleep and retention modes Support for up to 15 trained states/frequencies Flexible implementation to support Package-On-Package (PoP) or discrete DRAM-on-PCB systems with optimized PHY architecture Built-in anti-aging features to prevent effects of NBTI & HC

Tech Specs

Market SegmentAutomotive, Communications, Consumer Electronics, Data Processing, Industrial and Military Civil Aerospace, Others
FoundryTSMC
Geometry nm16, 7
Maturity Available on request

Features

  • Low latency, small area, low power
  • Compatible with JEDEC standard LPDDR5 SDRAMs up to 6400 Mbps
  • Compatible with JEDEC standard LPDDR4 and LPDDR4X SDRAMs up to 4267 Mbps
  • DFI 5.0 compliant interface to the memory controller – LPDDR5 DFI Frequency Ratio Support: DFI 1:1:4, 1:1:2 modes (DFICLK:CK:WCK) – LPDDR4 / LPDDR4X DFI Frequency Ratio Support: DFI 1:2, 1:4 mode support
  • Flexible channel architecture – 16- or 32-bit data path widths, supporting either single x32 channel or two x16 channels – 64-bit support, supporting two x32 channels
  • Support for byte-mode DRAM devices for high capacity systems
  • Support for many DRAM packaging options: – SDRAM components soldered directly to PCB – Package on Package PoP devices
  • PHY independent, firmware-based training using an embedded calibration processor – Utilizes specialized hardware acceleration engines – Supports: – Command Bus Training (VREF and Delay) – Write Leveling, Read Gate Training – Write/Read Training: – Per-bit DQS to DQ centering and per-bit deskew – Per-rank VREFDQ training on DRAM DQ bits – Periodic retraining for DRAM write (tDQS2DQ) and read (tDQSCK) drift – IO calibration and ODT calibration 3
  • Optional Decision Feedback Equalization (DFE) included for improved timing margins
  • Support for up to fifteen distinct trained states/frequencies to permit fast frequency changes
  • Each trained state can have unique frequency, I/O drive, and ODT impedance settings
  • Multiple inactive idle states including: – DFI_LP Mode: most clocks and delay lines gated – PHY Inactive: leakage only – PHY Retention: Core power removed, most I/Os powered down, SDRAMs held in self-refresh
  • Includes a low-jitter PLL for both PHY clock generation and SDRAM clock generation – Only one PLL is required per DDR PHY
  • Support for write/read preamble/postamble settings specified by JEDEC
  • SW controllable DQ bit and AC bit swizzling
  • Supports PHYs that go around a die corner and support for both East-West and North-South orientations
  • Includes the PHY Utility Block (PUB) – Soft IP Verilog design that includes PHY control features, such as read/write leveling and data eye training – APB and JTAG interfaces for register access
  • Test support: – At-speed loopback testing on both the address and data channels – Delay line BIST – MUX-scan ATPG (stuck-at SCAN) – PLL lock test – ZQ calibration test
  • Facilitates a JTAG register interface for easy test access
  • Firmware-based 2D eye mapping diagnostic tool allows measuring 2D eye for every bit of the bus at both DRAM and
  • host receivers
  • Direct override programming available for all VREF, ODT, drive strength, and timing delays to facilitate debug and characterization
  • Automotive grade PHYs in development

Deliverables

  • Executable .run installation file which includes GDSII, LEF files, LVS netlists, .lib/.db timing models, Verilog model, DRC/LVS log files, I/O IBIS Model, I/O HSPICE netlist, parameterized Verilog top-level PHY netlist files, sample Verification Environment, PHY data book, physical implementation guide, app notes, verification guide, installation guide, and implementation checklist
  • PUB includes Verilog code, Synthesis/ STA constraints and scripts, sample verification environment, and data book
  • Implementation Guide, Application notes, and quick start manuals
  • Firmware for training, ATE test and diagnostics
  • DDR PHY compiler • Support for PHY emulation
  • Optional deliverables include: &ndash, Signal integrity consulting services &ndash, PHY hardening consulting services &ndash, Subsystems consulting services &ndash, IP Prototyping kit for FPGA-based prototyping

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