The H.264/AVC Decoder (CWvc06) is an IP core that decodes H.264/AVC video streams in real-time for the Constrained Baseline Profile.
The core includes the H.264/AVC decoder software and the Coreworks silicon proven processor based hardware platform (CWda2211).
Operation in real-time is guaranteed for H.264 video stream with resolutions up to 1920x1080p@30fps with “zero” decoding latency.
The software is compiled into an image file (.bin) which can be automatically boot-loaded through one of the control interfaces (parallel AMBA APB or serial SPI) and run on the hardware platform with simple parameters setting.
The program can be configured, controlled and monitored by means of a configuration, control, and status register file, accessed by the control interface.
The Video Data (H.264/AVC stream) must be grouped in NAL units and is inputted using the parallel interface (PTDM). The Decoded Video is outputted using another parallel interface or optionally a shared memory buffer.
The interface to the external memory can be one of the following: AMBA AXI (for ASICs or Xilinx FPGAs), Avalon (for Altera FPGAs) or native MIG (for Xilinx FPGAs).
The Multimedia Platform can be expanded to perform audio and video decoding in a single AV sub-system. Some examples of supported audio formats are AAC-LC, HE-AAC, HE-AACv2, AAC-LD, AAC-ELD, AAC-ELD delay-reduced mode and MPEG-1/2.