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Compact, ultra-low power ARC EM processors and ASIL-Ready ARC EM Safety Island IP feature excellent code density

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Overview

The DesignWare® ARC® EM Family of embedded processors is based on the scalable ARCv2 Instruction Set Architecture (ISA) and is optimized for energy and performance efficiency (DMIPS/mW and DMIPS/mm2). The ARC EM family includes the EM4 (cacheless) and EM6 (instruction and data caches) processor cores, designed for use in power and area-sensitive embedded applications. They offer industry-leading performance efficiency of up to 1.81 DMIPS/MHz, with minimal area and power consumption.

The ARC EM DSP family, which includes the ARC EM5D, EM7D, EM9D and EM11D processors, are specifically designed for ultra low-power embedded DSP applications. The EM DSP processors are based on the enhanced ARCv2DSP ISA, which adds over 100 optimized DSP instructions to the area- and code-efficient real-time ARCv2 RISC ISA. The processors feature a power-efficient unified 32x32 MUL/MAC unit, support for fixed point DSP vector and single instruction multiple data (SIMD) operations. The new ISA includes support for the following classes of DSP instructions and operations: basic saturating arithmetic, vector unpacking, accumulators, as well as a broad selection of MAC operations.

ARC EM Safety Island IP is a family of dual-core lockstep processors that simplifies development of safety-critical applications and accelerates ISO 26262 certification of automotive system-on-chips (SoCs). The family includes ASIL D Ready certified ARC EM4SI and EM5DSI processors that integrate a self-checking safety monitor as well as hardware safety features such as error correcting code (ECC) and a programmable watchdog timer to help detect system failures and runtime faults. The ARC EM Safety Islands are supported by comprehensive safety documentation, including failure modes, effects and diagnostic analysis (FMEDA) reports that facilitate chip- and system-level ISO 26262 ASIL D compliance.

All of the EM Processors are highly-configurable and extensible, enabling designers to implement each core with the optimum combination of performance, code density, area and power consumption for the specific task or application. In addition, ARC Processor EXtension (APEX) technology offers designers the ability to create user-defined instructions, enabling the integration of custom hardware accelerators that improve application-specific performance while reducing power consumption and the amount of memory required.

The EM Family is supported by a robust ecosystem of software and hardware development tools, including an easy to use and low-cost ARC EM Starter Kit for early software development, the MQX real-time operating system (RTOS), and a portfolio of third-party tools, operating systems and middleware from leading industry vendors through the ARC Access Program as well as a comprehensive suite of free and open source software available through the embARC Open Software Platform.

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