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ULP fractional-N ADPLL for Bluetooth Low Energy transceivers in 55nm CMOS

All Silicon IP

Overview

This All Digital Phase-Locked Loop (ADPLL) IP block is a fully industrialized frequency synthesizer for Bluetooth® transceivers, designed in TSMC 55nm CMOS process. It features a high-performance synthesizer with GFSK modulator, while having a low silicon area, good suppression of disturbances from e.g. DC-DC converters or PAs, ultra-low power consumption, and several features that minimizes production test time. The IP is silicon proven and in mass production.

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